Automatic test pattern generation (ATPG) refers to the process in which logical patterns or vectors are generated. The test patterns can be applied to the logic (such as a portion of an integrated circuit) to test the functionality of the logic using internal scan chains. ATPG generally occurs by examining the net list of a circuit and generating a fault list. A fault list is a description of potential faults that can occur in the design and includes all nodes in the circuit. Different fault models can be used, such as the bridging fault model, the transition fault model, and the stuck at fault model. The stuck at fault model is the predominately used model. “Stuck-at-1” means that a certain node is always 1. “Stuck-at-0” means that a certain node is always 0. For example, in case of targeting a stuck-at-0 fault, the pattern will be generated such that a respective node is driven to 1 (also called sensitized) and propagated to an observable output. Based on the observable output, it is determined whether the node is actually driven to 1. If not, then a stuck-at-0 fault is present. To enable a node to be sensitized and propagated, not all bits of a test pattern need to be specified. The specified bits are referred to as “care” bits and the unspecified bits are called “don't care” bits.
Recently, the amount of data required to represent the test patterns in ATPG has increased substantially for a number of reasons. For example, the growing complexity of new fault models and the increasing sophistication of circuits being tested has increased the amount of data required to represent test patterns. Thus, the amount of memory of automatic test equipment (ATE) used to apply test patterns to circuits must be increased to compensate for the increase in test pattern data.
On-chip decompression of test patterns and compression of test results (by, for example, Design-for-Test (DFT) products) have been implemented to address the increase in test pattern data. However, on-chip compression and decompression is problematic for a number of reasons. First, the on-chip compression and decompression require a degree of overhead thereby increasing the size of the die and reducing the throughput. Moreover, increasing the die size results in a rapid reduction in yield (i.e., a larger die is more likely to be defective). Secondly, the on-chip compression and decompression functionality must be designed into the chip and suitably verified in the same manner as any other functional portion of the chip. Accordingly, the on-chip compression and decompression functionality adds a degree of technical risk to chip development that is disadvantageous. Moreover, many of the proposed on-chip compression techniques impact diagnostic capabilities and cannot deal very well with unknown test responses.